8-bitCPU
An 8-bit processor built from scratch, starting at the ALU, to understand computer architecture from the inside.
- 2024
- Personal project
- Computer architecture
- Architecture · Digital logic · ALU
You can spend an entire career in embedded systems treating the processor as a black box. This project was the opposite: building an 8-bit CPU starting from the arithmetic logic unit, to find out what is inside.
The ALU came first, in a separate repository. It is the piece that computes, and building only that already forces you to face carry propagation, two’s complement, and the flags the rest of the machine uses to decide what to do next.
The CPU came after: registers, datapath, instruction decoding, and the fetch-execute cycle tying it all together.
Why it matters to the rest of the portfolio
When you write firmware knowing what happens between fetching an instruction and executing it, decisions that looked arbitrary, why this operation costs more cycles, why this interrupt has that latency, start having an explanation.
What is inside
I built it in the Digital simulator, following the SAP-1 architecture. The blocks communicate over an 8-bit bus, and who gets to write to it at any moment is decided by tri-state drivers. Without them, two components write at once and the signals short.
The control unit is a ring counter of four D flip-flops in a loop, and it is what produces the four phases of every instruction. The program counter loads the address into the address register, program memory hands the instruction to the instruction register and the counter increments, the address field of the instruction fetches the operand from data memory, and the ALU executes and stores the result in the accumulator.
Each instruction is 8 bits, 3 of opcode and 5 of operand address. There are eight operations: add, subtract, multiply, divide, shift both ways, NAND and XOR. On shifts the address field is ignored and the ALU works on the accumulator alone. Memory is split into two EEPROMs, 16 positions for program and 32 for data.
The example program runs a sequence of add, multiply, shift left, subtract, shift right and divide, and you can watch the accumulator and the MQ register change every cycle. There are no conditional branches and no indirect addressing. The point was to show the minimum path of fetch, decode and execute, not to build a programmable machine.